1. Field of the Invention
The present invention relates to a multi-chip semiconductor package which has an improved integration by superposing several semiconductor chips, and more particularly to a multi-chip semiconductor package which is capable of having the thinnest structure by using a TAB technology (Tape Automated Bonding Technology) and a C-4 bonding technology.
2. Description of the Prior Art
Recently, a semiconductor package tends to be miniaturized, that is, be light and thin, while a bare chip gradually becomes larger in size so that an area or a volume ratio of the bare chip to an overall semiconductor package increases. Accordingly, a technology for manufacturing a semiconductor package is gradually converted from the conventional plastic packaging technology in which a chip is placed on a paddle to LOC (Lead-On-Chip) technology in which leads are placed on a chip. Also, a semiconductor package is usually equipped with one bare chip, but it is well known that a multi-chip semiconductor package is manufactured by superposing several chips in order to form a piggy-bag type package or by superposing several chips inside a semiconductor package (disclosed in the Nikkei Micro Devices, April, 1991).
Referring to FIG. 1, there is shown a perspective view representing a typical embodiment of a conventional multi-chip semiconductor package which has the piggy-big type. As shown in FIG. 1, a plurality of semiconductor packages 2 are superposed on the lowermost semiconductor package 1 and outer leads 2a attached to upper semiconductor packages 2 are bonded to outer leads 1a attached to the lowermost semiconductor package 1 in a conventional manner so that the outer leads 1a and 2a are electrically connected to the another. The outer leads 1a of the lowermost semiconductor package 1 are outwardly formed into a SOP (Small Outline Package) type and fitted in a memory module or a board level. Therefore, the conventional piggy-bag type of semiconductor package has an improved integration 3 dimensionally.
However, since the conventional semiconductor package is constructed such that the semiconductor packages 1 and 2 each of which was made separately are superposed, the conventional semiconductor package has disadvantage in that each semiconductor package increases in a thickness by an increased wire loop height owing to a wire bonding and a mold thickness of encapsulation epoxy resin, thereby causing the thickness of the whole semiconductor packages to inevitably increase.
On the other hand, referring to FIG. 2, there is shown a cross sectional view representing a construction of a conventional multi-chip semiconductor package in which upper and lower bare chips are laterally arranged in parallel to each other in a single semiconductor package.
With reference to FIG. 2, the manufacturing process of the multi-chip semiconductor package is described as follows. First, two bare chips 3 and 4 are connected to each other. Inner leads to TAB tapes 5 and 6 are bonded to bumps 8 provided at pad portions of the bare chips 3 and 4 by the TAB technology. Outer leads of the TAB tapes 5 and 6 are bonded to lead frames 9 and 9', respectively. Finally, a mold portion 10 enveloping the resulting chip assembly is formed by applying an epoxy resin. Accordingly, a single semiconductor package has two bare chips 3 and 4 therein, thereby improving the integration of the elements and miniaturizing the package, that is, allowing the package to be light and to be thin.
In addition, referring to FIG. 3, there is shown a cross sectional view representing another embodiment of conventional multi-chip semiconductor packages in which four bare chips 11, 12, 11a and 12a are embedded therein.
In a similar manner to that described in FIG. 2, the multi-chip semiconductor package shown in FIG. 3, is manufactured as follows. In the upper half part of the multi-chip semiconductor package, the upper and lower bare chips 11 and 12 are connected to each other. Inner leads of TAB tapes 15 and 16 are bonded to bumps 13 and 14 of the chips 11 and 12, respectively. The bumps 13 and 14 are provided at opposite ends of upper and lower surfaces of the chips 11 and 12, respectively. Outer leads of the TAB tapes 15 and 16 are bonded to lead frames 17 and 17', respectively. At the same time, in the lower half part of the multi-chip semiconductor package, an upper bare chip 11a and a lower bare chip 12a are connected to each other. Inner leads of TAB tapes 20 and 21 are bonded to bumps 18 and 19 provided at opposite ends of upper and lower surfaces of the upper and lower bare chips 11a and 12a. Outer leads of the TAB tapes 20 and 21 are bonded to the lead frames 17 and 17' , respectively. Finally, a mold portion 22 enveloping the resulting chip assembly is formed as applying the encapsulation epoxy resin. Accordingly, a single semiconductor package has four bare chips 11, 12, 11a and 12a therein, thereby more improving its integration and more miniaturizing the package than that shown in FIG. 2.
However, in the above-mentioned multi-chip semiconductor packages shown in FIG. 2 and FIG. 3, since the inner leads of the TAB tapes 6 and 15, 16, 20, 21 are bonded to the bumps 7, 8 and 13, 14, 18, 19 provided at upper and lower surfaces of the bare chips 3, 4 and 11, 12, 11a, 12a, the heights H and H', the one between the upper TAB tape 5 and the lower TAB tape 6 and the other between the upper TAB tape 15 and the lower TAB tape 21, increase, thereby causing a thickness of the whole semiconductor packages to increase.
Also, since the numbers of the TAB tapes 5, 6 and 15, 16, 20, 21 increase, a manufacturing cost of the multi-chip semiconductor package increases and a complex process is obliged to be required for manufacturing the package.
In addition, since each inner lead bond (ILB) between the bare chips 3, 4, 11, 12, 11a, and 12a and the TAB tapes 5, 6, 15, 16, 20, and 21 is formed at an outer surface of the bare chips 3, 4, 11, 12, 11a, 12a, the multi-chip semiconductor packages are not proper for the LOC technology. Due to relatively short lengths of the TAB tapes 5, 6, 15 and 16, a bonding process of the inner lead bonds is complex and a handling thereof is not easy.